Design Methodologies Forum

 

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Design and Implementation of Signal Processing Systems

Technical Committee

A Forum on Design Methodology

To bootstrap the research in the area of design techniques and methodologies for Signal Processing Systems to the next level of complexity, it is essential that the many excellent research results, currently available, get a wide dissemination to the complete community. This forum intends to be an enabler for this to happen. If you have any tools related to Signal Processing system design you would wish to distribute, you can place an "advertisement" and pointer on this page. The same is true for benchmark sets, design frameworks, etc.

The success of this effort is obviously dependent upon your cooperation. If you have anything to post, please send e-mail to vspforum@walhalla.eecs.berkeley.edu stating the area of your contribution and the access mechanism (www-pointer or ftp-address).

Forum Corners

Simulation and System Modeling

  • Ptolemy (U.C. Berkeley) is a system-level design frame-work for signal processing systems that allows for the mixing of different models of computation.

Hardware Compilation

  • GAUT, High-Level Synthesis tool - from algorithm to RTL architectures

Software Compilation

  • no postings so far...

Synthesis and Exploration

  • HYPER (U.C. Berkeley) is a synthesis and design exploration environment for DSP ASICS. The environment operates under UNIX and X-windows. Object code is only available for SUN workstations.
  • HIFI (Delft University) is an architectural mapping tool, targeting a range of applications and architectures. An example of how HIFI can be used to map a class of algorithms - called Jacobi algorithms - onto an array of processors can be accessed as well.
  • ARREST (University of Massachusetts) is a tool for visualizing and estimating array computations used in arithmetic, coding, DSP and communications.

Hardware/Software Co-design

  • No postings so far...

DSP Benchmarks

  • BDTImark benchmark by Berkeley Design Technology Inc. (BDTI) is a benchmark of 11 assembly language kernels. The kernels are hand optimized and use only on-chip memory. They do test memory bandwidth.
  • A complementary benchmarking effort tests the performance of the compiled C code. This benchmarking effort is by a consortium of more than 30 companies organized by Electronic Data News (EDN) called the EDN Embedded Microprocessor Benchmark Consortium. They have developed a variety of benchmarks for embedded processors (microcontrollers, DSPs, etc.) for different application spaces (automotive-industrial, consumer, office automation, networking and telecommunications).

Libraries

  • The MSU Standard Cell Library (Mississippi State University) contains an extensive library of standard cells, targeted at the MOSIS SCMOS design rules. The homepage provides ample information regarding the use of the library.
  • The LAGER Library (U.C. Berkeley) contains libraries targeted for a variety of implementation styles, including macrocells, datapaths and standard cells. The latest offering includes a low-power library targeted at low-voltage operation.

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