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DSP/FPGA Engineer (Mid-to-Senior Level Position)
Are you seeking a truly creative, challenging technical opportunity? Does product development excite you more than filling out a timecard? Does working in a tightly integrated hardware and software team where thinking outside the box is rewarded sound exciting? Do you want to be a part of a high visibility effort to create a next-generation Counter UAS (C-UAS) system and get paid to work with drones?
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A full time one-year position as a postdoctoral Fellow is available at the AViReS Lab ( https://avires.dimi.uniud.it ) of the Department of Mathematics, Computer Science and Physics (DMIF), University of Udine.
Section: Events
Publication: IEEE Journal of Selected Topics in Signal Processing
Manuscript Due: February 26, 2021
Publication Date: November 2021
CFP Document
