PhD student on Error-Correction Coding for Ultra-Reliable Low-Latency Communications Systems

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PhD student on Error-Correction Coding for Ultra-Reliable Low-Latency Communications Systems

Eindhoven University of Technology
Country of Position: 
Contact Name: 
Alexios Balatsoukas-Stimming
Subject Area: 
Machine Learning for Signal Processing
Design and Implementation of Signal Processing Systems
Start Date: 
June 20, 2019
Expiration Date: 
September 01, 2019
Position Description: 

Motivated by Shannon's channel coding theorem, error-correction coding has become an integral part of all modern communications systems and standards that have enabled the information revolution of the past decades. Recently, there has been a growing interest in mission-critical applications that have extremely stringent reliability and latency constraints, such as autonomous driving, industrial automation, and remote robotic surgeries. The systems used in these applications are referred to as ultra-reliable low-latency communications (URLLC) systems in the context of the newly-introduced 5G communications standard. The most common way to enable ultra-low-latency communications is to use very short data packets that are only, e.g., 64 or 128 bits long. Unfortunately, modern error-correcting codes are typically designed for (and are hence most effective for) long data packets. For this reason, the design of error-correcting codes and corresponding decoding algorithms that specifically target short packets is a research topic that is garnering significant attention.

For example, the short packets that are used in URLLC systems enable the use of novel and exotic decoding algorithms with very strong reliability guarantees that would otherwise be infeasible in terms of their implementation complexity. The efficient hardware implementation of these decoding algorithms as well as their adaptation to specific classes of error-correcting codes is an important open research direction. Moreover, the design of optimal (semi-)random error-correcting codes and decoders using non-linear optimization or machine learning techniques also becomes feasible when using short packets.

The general focus of this project is on the design of error-correction coding schemes, decoding algorithms, and hardware architectures for URLLC systems. The successful candidate for this PhD position will have significant freedom (and will receive the appropriate guidance) to shape the exact research agenda of the project.

Job requirements

We are looking for candidates that match the following profile:

  • A master’s degree (or equivalent) in Electrical Engineering or related disciplines
  • Good knowledge of communications systems and, in particular, error-correcting codes.
  • Good knowledge of hardware design on an RTL level (e.g., VHDL or Verilog).
  • General working knowledge of programming (e.g., MATLAB, Python).
  • Familiarity with ASIC design (e.g., synthesis, place and route) would be beneficial.
  • Familiarity with machine learning techniques and tools would be beneficial.
  • Good communication and organization skills, ability to work in a team, positive and proactive problem-solving attitude.
  • Excellent English language skills (writing and presenting).

Details on the conditions of employment and the application method can be found here.

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